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ADT7490
Table 101. REGISTER 0x81 ? INTERRUPT STATUS REGISTER 4 (POWER-ON DEFAULT = 0x00)
Bit No.
[2:0]
[3]
[4]
[5]
[6]
[7]
Mnemonic
RES
PECI1
PECI2
PECI3
I MON
V TT
R/W
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Description
Reserved
A Logic 1 indicates that the PECI high or low limit has been exceeded by the PECI value
from PECI Client Address 0x31. This bit is cleared on a read of the status register only if the
error condition has subsided.
A Logic 1 indicates that the PECI high or low limit has been exceeded by the PECI value
from PECI Client Address 0x32. This bit is cleared on a read of the status register only if the
error condition has subsided.
A Logic 1 indicates that the PECI high or low limit has been exceeded by the PECI value
from PECI Client Address 0x33. This bit is cleared on a read of the status register only if the
error condition has subsided.
A Logic 1 indicates that the I MON high or low limit has been exceeded. This bit is cleared on a
read of the status register only if the error condition has subsided.
A Logic 1 indicates that the V TT high or low limit has been exceeded. This bit is cleared on a
read of the status register only if the error condition has subsided.
Table 102. REGISTER 0x82 ? INTERRUPT MASK REGISTER 3 (POWER-ON DEFAULT = 0x00) (Note 1)
Bit No.
[0]
[1]
[2]
[3]
[6:4]
[7]
Mnemonic
PECI0
DATA
COMM
OVT
RES
OOL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
A Logic 1 masks SMBALERT assertions for out-of-limit conditions on PECI0.
A Logic 1 masks SMBALERT assertions for PECI data errors.
A Logic 1 masks SMBALERT assertions for PECI communications errors.
OVT = 1 masks SMBALERT for overtemperature THERM conditions.
Reserved
OOL = 1 masks SMBALERT assertions when the OOL status bit is set.
Note that the OOL mask bit is independent of the individual mask bits of Interrupt Mask
Register 4 (0x83). Therefore, if the intention is to mask SMBALERT assertions for any of the
Interrupt Status Register 4 bits, OOL must also be masked.
1. If the mask bits in Register 0x82 are set, it is also necessary to set the OOL mask bit in Register 0x75 to ensure the SMBALERT output is
not asserted.
Table 103. REGISTER 0x83 ? INTERRUPT MASK REGISTER 4 (POWER-ON DEFAULT = 0x00) (Note 1)
Bit No.
[2:0]
[3]
[4]
[5]
[6]
[7]
Mnemonic
RES
PECI1
PECI2
PECI3
I MON
V TT
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
A Logic 1 masks ALERT assertions for out-of-limit conditions on PECI1.
A Logic 1 masks ALERT assertions for out-of-limit conditions on PECI2.
A Logic 1 masks ALERT assertions for out-of-limit conditions on PECI3.
A Logic 1 masks ALERT assertions for out-of-limit conditions on I MON .
A Logic 1 masks ALERT assertions for out-of-limit conditions on V TT .
1. If the mask bits in Register 0x83 are set, it is also necessary to set the OOL mask bit in Register 0x82 to ensure the SMBALERT output is
not asserted.
Table 104. V TT , I MON LIMIT REGISTERS
Register Address
0x84
0x85
0x86
0x87
R/W (Note 1)
R/W
R/W
R/W
R/W
Description
V TT Low Limit
I MON Low Limit
V TT High Limit
I MON High Limit
Power-On Default
0x00
0x00
0xFF
0xFF
1. These registers becomes read-only when the Configuration Register 1 (0x40) Lock bit is set to 1. Any subsequent attempts to write to these
registers fail.
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